Information of ADC
What is an ADC? The ADC converter is a system that converts analog signals into digital signals. It is a process of filtering, sample-and-hold, quantization and encoding. The analog signal passes band-limited filtering, sample-and-hold circuit, and becomes a ladder-shaped signal, and then passes through the encoder to make each level in the ladder-shaped signal become a binary code. Finally, the analog quantity is converted into a digital quantity and then transmitted to the CPU. That is to say, almost all energized data need ADC conversion. For example, electric energy metering of electric energy meters, weight measurement of electronic scales, temperature measurement of electronic thermometers, and communication fields.
Which is the Best ADC?
After years of development and continuous technological innovation, ADC converters have developed from Flash ADCs, Successive-Approximation ADCs, Counting/Slope Integration ADCs to sigma-delta (Σ-Δ) ADCs and Pipelined ADCs. They have their own advantages and disadvantages, and they can also meet different requirements.
Successive-Approximation ADCs, Counting/Slope Integration ADCs and compression ADCs, etc. are mainly used in low-speed or medium-speed, medium-precision data acquisition and intelligent instruments. Hierarchical and pipelined ADCs are mainly used in high-speed signal processing, fast waveform storage and data recording, etc., such as video signal quantization and high-speed digital communication technology. ∑-△ ADC is mainly used in high-precision data acquisition, especially in electronic measurement fields such as digital sound systems, multimedia, seismic exploration instruments, sonar and so on. Here a brief description of the main ADC types is given below.
The successive-approximation ADC is widely used. It includes a comparator, a digital-to-analog converter, a successive-approximation register (SAR) and a control logic unit. It is to continuously compare the sampling input signal with the known voltage. One clock cycle completes the 1-bit conversion, and the N-bit conversion requires N clock cycles. The conversion is completed and the output binary number is output. The resolution and sampling rate of this type ADC are contradictory: when the ADC resolution is low, the sampling rate is high, and if the resolution is to be improved, the sampling rate will be limited.
Advantages: when the resolution is lower than 12 bits, the price is cheap, and the sampling rate can reach 1MSPS. Compared with other types, the power consumption is quite low.
Disadvantages: In the case of higher than 14-bit resolution, the price is higher. The signal generated by the sensor needs to be conditioned before analog-to-digital conversion, including gain stage and filtering, so that the cost will increase significantly.
Counting/Slope Integration ADCs
Counting/Slope Integration ADC is also called dual-slope or multi-slope ADC, and its applications are also very wide. It is composed of an analog integrator with an input switch, a comparator and a counting unit. The input analog voltage is converted into a time interval proportional to its average value through two integrations. At the same time, a counter is used to count the clock pulses in this time interval, so as to realize the analog-to-digital conversion. Because the input end applies the integrator, it has a strong ability to suppress the interference of AC noise. For example, for high-frequency noise and fixed low-frequency (50Hz or 60Hz) interference suppression, it is suitable for use in noisy industrial environments. This type ADC is mainly used in low-speed, precision measurement and other fields, such as digital voltmeters.
Advantages: High resolution, up to 22 bits; low power consumption and low cost.
Disadvantages: The conversion rate is low, 100~300SPS at 12 bits.
The main feature of inter ADC is fast speed, which is the fastest of all types. The sampling rate can reach above 1GSPS. However, due to the limitations of power and volume, it is difficult to improve the resolution. The conversion of all bits of the ADC with this structure is completed at the same time, and the conversion time mainly depends on the switching speed of the comparator and the transmission time delay of the encoder. In addition, increasing the output code has little effect on the conversion time, but as the resolution increases, a high-density analog design requires large number of precision divider resistors and comparator circuits for the conversion. That is to say, the output number is increased by one bit and the number of precision resistors is increased. It is about to double, and the comparator is also approximately doubled.
The resolution of the parallel comparison ADC is limited by die size, input capacitance, power, etc. If the accuracy of the parallel comparators does not match, it will also cause static errors and increase the input offset voltage.
Sigma-delta (Σ-Δ) ADCs
The Sigma-delta (Σ-Δ) ADC is composed of an integrator, a comparator, a 1-bit DA converter, and a digital filter. In principle, it is similar to the integral type. The input voltage is converted into a time (pulse width) signal and processed by a digital filter to obtain a digital value.
A/D Converter ICs
There are many ADC ICs available in the market which can be used along to do conversion. Here lists several ADC ICs and their features and specifications as ADC selection references.
Specifications of AD7621
Here are some specifications of AD7621
16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC, High sampling rate, Available in a 48-lead LQFP or a 48-lead LFCSP
- 16 Bits Resolution with No Missing Codes
- No Pipeline Delay ( SAR architecture )
- Differential Input Range: ±VREF (VREF up to 2.5V)
3 MSPS (Wideband Warp and Warp Mode)
2 MSPS (Normal Mode)
1.25 MSPS (Impulse Mode)
- INL ±2 LSB Max (±30 ppm of FS)
- SINAD: 89 dB Typ @ 100 kHz
- THD: -103 dB Typ @ 100 kHz
- Parallel (16 or 8 bits bus) and Serial 5 V/3.3 V/2.5 V Interface
- SPI®/QSPI™/MICROWIRE™/DSP Compatible
- On-board Low Drift Reference with Buffer and Temperature Sensor
- Single 2.5 V Supply Operation
- Power Dissipation: 70 mW Typ @ 3 MSPS With REF
18-Bit, 2 MSPS, Charge Redistribution SAR ADC
- 18-bit resolution with no missing codes
- 5 V internal low drift reference
2 MSPS (Warp mode)
1.5 MSPS (Normal mode)
- Differential input range: ± VREF (VREF up to 2.5 V)
- INL: ±2 LSB typical
- No pipeline delay (SAR architecture)
- Parallel (18-, 16-, or 8-bit bus)
- Serial 5 V/3.3 V/2.5 V interface
- SPI®/QSPI™/MICROWIRE™/DSP compatible
- On-board low drift reference with buffer and temperature sensor