Table of Contents

Introduction

How to Design Counters Using Sequential Circuits? We already know that counters can be implemented like cascaded flip-flop stages and some gate logic where each stage divides a number of incoming pulses by two. To keep our example simple, we’ll choose a small counter size, but also show how the design can be extended to larger sizes. Specifications for the counter is:

The counting order is 0, 1, 2,… 6, 7, 0, 1,…
There is an input signal w.

The value of this signal is taken into account at each clock cycle. If w = 0, the current count remains the same; if w = 1, the count is incremented. A counter can be designed as a synchronous sequential circuit using design techniques introduced in previous sections

State Assignment

Three state variables are needed to represent eight states. Let these variables, denoting the current state is called y₂, y₁ and y₀. Let Y₂, Y₁ and Y₀ denote the corresponding next state function. The most easiest state assignment is to encode each state with a binary number that the counter have to provide output in that state. Then the desired output signals will be the same as the signals representing the state variables. This leads to the table of assigned state:

After assigning the A,B,….H to binary numbers.

The last step in the design is the selection of the type of flip-flops and the derivation of expressions that implement and control the flip inputs. The easiest option is to use type D flip flops. We are going to follow this approach. Then we will show the alternative of using JK type flip-flops. In both cases, the flip-flops must be edge-triggered to ensure that it only takes one transition place during one clock cycle.

Implementation using D-flipflop

When using D-type flip-flops to implement a finite state machine, each next-state function Yi, is connected to the D input of a flip-flop that implements the specific state variable yi. the next state functions are derived from this information. By using K-maps we get the following results:

D₀ = Y₀ = wy₀ + wy₀

D₁ = Y₁ = wy1 + y₁y₀ + wy₀ _y1

D₂ = Y₂ = wy₂ + y₀ y₂ + y₁ y₂ + wy0y1y2

It is not clear how to expand this range implement a larger counter because no clear pattern is discernible in the expressions for D0, D1 and D2. However, these expressions can also be written as:

D₀ = wy₀ + wy₀

= w ⊕ y₀

D₁ = wy₁ + y₁ y₀ + wy₀ y₁

= (w + y₀) y₁ + wy₀ y₁

= wy0y1 + wy₀y₁

= wy₁ ⊕ y₁

D₂ = wy₂ + y₀ y₂ + y₁ y₂ + wy₀ y₁ y₂

= (w + y₀ + y₁) y₂ + wy₀ y₁ y₂

= wy₁ y₁ y₂ + wy₀ y₁ y₂

= wy₀ y₁ ⊕ y₂

Karnaugh maps for Dflip-flops for the counter. — Karnaugh maps for D flip-flops for the counter.

Circuit diagram for the counter implemented with D flip-flops

Implementation using J-K flipflop:

JK flip flops are an attractive alternative. Using these flip-flops to implement the sequential circuit requires the derivation of the J and K inputs for each flip flops. The following check is required:

If a flip-flop is in the state 0 it has to remain in the state 0, then the J = 0 and K = d (where d means that K could be equal to either 0 or 1). • If the flip-flop in state 0 changes its state into 1, then J = 1 and K = d.
If a flip-flop in state 1 is to remain in state 1, then J = d and K = 0.
If the flip-flop is in state 1 is to change to state 0, then J = d and K = 1.

Following these instructions, we can create a truth table that specifies the desired values of inputs J and K for the three flip-flops in our design. a modified version of the state-assigned table with input functions J and K included. To see how this table is derived, consider the first row in which the current state is y2y1y0 = 000. If w = 0, then the next state is also Y2Y1Y0 = 000. the value of each flip-flop is 0 and should remain 0.

This means that checking J = 0 and K = d for all three flip-flops. We continue in the first line, if w = 1, the next state will be Y2Y1Y0 = 001. So flip-flops y2 and y1 still remain at 0 and have control J = 0 and K = d. However, flip-flop y0 must change from 0 to 1, which is achieved with J = 1 and K = d.

The rest of the table is derived in the same way by considering each gift state y2y1y0 and providing the necessary control signals to achieve the new state Y2Y1Y0. A state-assigned table is essentially a state table in which each state is encoded state variables.

When D flip-flops are used to implement the FSM, the next state items in the state-assigned table correspond directly to the signals that must be applied to D inputs. This does not apply if another type of flip-flops is used.

The table that gives status information in the form of flip-flop inputs that must be “excited” to cause the transitions to the next states are usually called the excitation table. Wake-up table shows how JK flip-flops can be used.

In many books the term excitation table is used even when D flip-flops are involved, in which case it is synonymous with state-assigned table. Once has been derived, it provides a truth table with inputs y2, y1, y0 and w and outputs J2, K2, J1, K1, J0 and K0. We can then derive expressions for

J₀ = K₀ = w

J₁ = K₁ = wy₀

J₂ = K₂ = wy₀y₁

Excitation table for the counter with JK flip-flops.

The k-map of the expression is given below:

Karnaugh maps for JK flip-flops in the counter.

The logic diagram is given below:

Using the factored form, the counter circuit can also be implemented. Note that in this circuit all the steps (except the very first one) look the same. Also note that this circuit has the same structure like the previous circuit because it connects the J and K inputs of the flip-flop together they change the flip-flop to a T flip-flop.

Factored-form implementation of the counter.

What are the Counters ? UP Counter Operation